1. Field of the Invention
The present invention relates to a non-volatile memory cell with asymmetrical doping profile for source and drain regions.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Many types of EEPROM and flash memories utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to source line 128. Select gate 120 is controlled by applying the appropriate voltages to select line SGD. Select gate 122 is controlled by applying the appropriate voltages to select line SGS. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate. For example, transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0.
Note that although FIGS. 1 and 2 shows four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, FIG. 3 shows three NAND strings 202, 204 and 206 of a memory array having many more NAND strings. Each of the NAND strings of FIG. 3 includes two select transistors and four memory cells. For example, NAND string 202 includes select transistors 220 and 230, and memory cells 222, 224, 226 and 228. NAND string 204 includes select transistors 240 and 250, and memory cells 242, 244, 246 and 248. Each NAND string is connected to the source line by its select transistor (e.g. select transistor 230 and select transistor 250). A selection line SGS is used to control the source side select gates (e.g., 230 and 250). The various NAND strings are connected to respective bit lines by select transistors 220, 240, etc., which are controlled by select line SGD. Word line WL3 is connected to the control gates for memory cell 222 and memory cell 242. Word line WL2 is connected to the control gates for memory cell 224 and memory cell 244. Word line WL1 is connected to the control gates for memory cell 226 and memory cell 246. Word line WL0 is connected to the control gates for memory cell 228 and memory cell 248. Each bit line and the respective NAND string(s) that are connected to that bit line via a bit line contact comprise the columns of the array of memory cells. The word lines (WL3, WL2, WL1 and WL0) comprise the rows of the array. Each word line connects the control gates of the memory cells in the row. For example, word line WL2 is connected to the control gates for memory cells 224, 244 and 250. The NAND strings connect to the bit lines via bit line contacts. Bit lines are shared with multiple NAND strings. Typically, the bit line runs on top of the NAND strings in a direction perpendicular to the word lines and is connected to sense amplifiers.
Each memory cell can store data (analog or digital). When storing one bit of digital data, the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data “1” and “0.” In one example of a NAND type flash memory, the voltage threshold is negative after the memory cell is erased, and defined as logic “1.” The threshold voltage after a program operation is positive and defined as logic “0.” When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored. When the threshold voltage is positive and a read operation is attempted, the memory cell will not turn on, which indicates that logic zero is stored.
A memory cell can also store multiple levels of information, for example, multiple bits of digital data. In the case of storing multiple levels of data, the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information is stored, there will be four threshold voltage ranges assigned to the data values “11”, “10”, “01”, and “00.” In one example of a NAND type memory, the threshold voltage after an erase operation is negative and defined as “11”. Positive threshold voltages are used for the states of “10”, “01”, and “00.”
Relevant examples of NAND type flash memories and their operation are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference: U.S. Pat. No. 5,570,315; U.S. Pat. No. 5,774,397; U.S. Pat. No. 6,046,935; U.S. Pat. No. 6,456,528; U.S. patent application. Ser. No. 09/893,277 (now U.S. Pat. No. 6,522,580); and U.S. patent application. Ser. No. 10/379,608 (now U.S. Pat. No. 6,859,397).
When programming a flash memory cell, a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel area under the floating gate are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised. To apply the program voltage to the control gate of the cell being programmed, that program voltage is applied on the appropriate word line. As discussed above, that word line is also connected to one memory cell in each of the other NAND strings that utilize the same word line. For example, when programming memory cell 224 of FIG. 3, the program voltage will also be applied to the control gate of memory cell 244 because both memory cells share the same word line. A problem arises when it's desired to program one cell on a word line without programming other cells connected to the same word line, for example, when it's desired to program memory cell 224 and not memory cell 244. Because the program voltage is applied to all memory cells connected to a word line, an unselected memory cell (a memory cell that is not to be programmed) on the same word line may become inadvertently programmed. For example, cell 244 is adjacent to cell 224. When programming cell 224, there is a concern that cell 244 might unintentionally be programmed. The unintentional programming of the unselected cell on the selected word line is referred to as “program disturb.” In some flash memory systems, a programming process will simultaneously program memory cells sharing a common word line that are on every other NAND string; therefore, the memory cells connected to that word line but on the unselected NAND strings can be subjected to program disturb.
Several techniques can be employed to prevent program disturb. In one method known as “self boosting,” the unselected NAND strings are electrically isolated from the corresponding bit lines and a pass voltage (e.g. 7-10 volts, but not limited to this range) is applied to the unselected word lines during programming. The unselected word lines couple to the channel area of the unselected NAND strings, causing a voltage (e.g., 6-10 volts) to exist in the channel of the unselected NAND strings, thereby reducing program disturb. Self boosting causes a boosted voltage to exist in the channel which lowers the voltage differential across the tunnel oxide and hence reduces program disturb. Note that the boosted channel voltage can vary largely since the boosted channel voltage depends on the value of the pass voltage and also on the state of the memory cells, with boosting being most efficient (highest channel voltage) when all memory cells in the NAND string are in the erased state.
FIGS. 4A and 4B depict NAND strings that are being programmed and inhibited using the self-boosting method. FIG. 4A depicts a NAND string being programmed. The NAND string of FIG. 4A includes eight memory cells 304, 306, 308, 310, 312, 314, 316 and 318. Each of those eight memory cells includes a floating gate (FG) and a control gate (CG). Between each of the floating gates are source/drain regions 330. At one end of the NAND string is a drain side select gate 324. The drain side select gate 324 connects the NAND string to the corresponding bit line via bit line contact 334. At another end of the NAND string is a source side select gate 322. Source side select gate 322 connects the NAND string to common source line 332. During programming, the memory cell selected for programming (e.g., memory cell 312) receives a program voltage Vpgm on its associated word line. The program voltage Vpgm can typically vary between 12 to 24 volts. In one embodiment, the program voltage signal is a set of pulses which increase in magnitude with each new pulse. A pass voltage Vpass of approximately 8 volts is applied to the control gates of the memory cells that are not selected for programming. Source side select gate 322 is in an isolating state, receiving a zero gate (G) voltage. A low voltage is applied to the common source line 332. This low voltage can be zero volts. However, the source voltage can also be slightly higher than zero volts to provide better isolation characteristics of the source side select gate. A voltage Vsgd, which is typically in the range of the power supply voltage Vdd (e.g., 2.5 volts), is applied to drain side select gate 324. Zero volts is applied to bit line contact 334 via the corresponding bit line to enable programming of the selected memory cell 312 string. Channel 340 is at or close to zero volts. Because of the voltage differential between the channel and the floating gate, electrons tunnel through the gate oxide (also commonly referred to as tunnel oxide) into the floating gate by Fowler-Nordheim tunneling.
The NAND string of FIG. 4B depicts a NAND string being inhibited from programming. The NAND string includes eight memory cells 350, 352, 354, 356, 358, 360, 362 and 364. The NAND string also includes drain side select gate 366 connecting the NAND string to the corresponding bit line via bit line contact 374, and source side select gate for 368 connecting the NAND string to common source line 332. Between each of the floating gate stacks are source/drain regions 370. The NAND string of FIG. 4B has Vsgd applied to the gate of the drain side select gate 366, zero volts applied to the gate of the source side select gate 368 and zero volts (or a slightly higher voltage) at the common source line 332. Bit line contact 374 receives the power supply voltage Vdd via the corresponding bit line in order to inhibit the programming of memory cell 358.
When Vdd is applied, the drain side select transistor 366 will initially be in a conducting state; therefore, the channel area under the NAND string will partly be charged up to a higher potential (higher than zero volts, but less than Vdd). This charging is commonly referred to as pre-charging. The pre-charging will stop automatically when the channel potential has reached a certain level given by Vsgd-Vt, where Vt equals the threshold voltage of the drain side select gate 366. After the channel has reached that potential, the select gate transistor is non-conducting. The voltages Vpass and Vpgm are ramped up from zero volts to their respective final values (not necessarily at the same time), and because the drain side select gate transistor 366 is in a non-conducting state, the channel potential will start to rise because of the capacitive coupling between the word lines and the channel area. This phenomenon is called self boosting. It can be seen from FIG. 4B that channel 380 is boosted, more or less uniformly, to a boosting voltage. Because the voltage differential between the floating gate of memory cell 358 and channel 380 has been reduced, programming is inhibited.
More information about programming NAND flash memory, including self boosting techniques, can be found in U.S. patent application Ser. No. 10/379,608, titled “Self Boosting Technique,” filed on Mar. 5, 2003 (now U.S. Pat. No. 6,859,397); and in U.S. patent application Ser. No. 10/629,068, titled “Detecting Over Programmed Memory,” filed on Jul. 29, 2003 (now U.S. Pat. No. 6,917,542), both are incorporated herein by reference in their entirety.
A NAND string is typically (but not always) programmed from the source side to the drain side, for example, from memory cell 304 to memory cell 318 (see FIG. 4A). When the programming process is ready to program the last (or near the last) memory cell of the NAND string, if all or most of the previously programmed cells on the string being inhibited were programmed, then there is negative charge in the floating gates of the previously programmed cells. Because of this negative charge on the floating gates, the boosting potential is reduced and there still may be program disturb on the last few word lines. This problem is exacerbated for multi-level memory cells since the programmed threshold voltage can be higher for multi-level memory cells, resulting in less boosting. One attempt to address this problem is Erased Area Self Boosting (“EASB”). EASB attempts to isolate the channel of previously programmed cells from the channel of the cell being inhibited.
In the EASB method, the channel area of the selected NAND string is divided into two areas. An area at the source side of the selected word line that can contain a number of programmed (or erased cells) memory cells and an area at the drain side of the selected word line in which the cells are still in the erased state. The two areas are separated by a word line that is biased to a low voltage, typically zero volts. Because of this separation, the two areas can be boosted to different potentials. In almost all cases, the area at the drain side of the selected word line will be boosted to a higher potential than the area at the source side. Since the highest boosted area is the area with the erased cells, this boosting method is referred to as Erased Area Self Boosting (EASB). FIGS. 5A and 5B depict the operation of EASB.
FIG. 5A shows a NAND string being programmed. The NAND string includes eight memory cells 404, 406, 408, 410, 412, 414, 416 and 418. Each of the eight memory cells includes a control gate (CG) and a floating gate (FG). The NAND string also includes a drain side select gate 424 connecting the NAND string to the corresponding bit line via bit line contact 444, and a source side select gate 422 connecting the NAND string to common source line 442. Between each of the floating gates are source/drain regions 440. Memory cell 412, selected for programming, will receive programming voltage Vpgm at its control gate. The source side neighbor, memory cell 410, will receive zero volts (or a potential close to zero) at its control gate. The remaining non-selected memory cells will receive Vpass at their control gates. The source side select gate is in an isolating state, typically receiving a zero volt gate voltage. A low voltage can also be applied to the common source line 442; however, it can also slightly higher to improve the isolation characteristics of source side select gate 422. A voltage Vsgd, which is typically in a similar range to supply voltage Vdd is applied to the gate of the drain side select gate 424. Zero volts is applied to the bit line contact via the corresponding bit line. Because the bit line is at zero volts, channel 446 will be at approximately zero volts. Because of the large differential voltage between the channel voltage and the floating gate voltage of memory cell 412, electrons will tunnel into the floating gate of memory cell 412, thereby, programming memory cell 412.
FIG. 5B depicts a NAND string being inhibited using EASB. The NAND string of FIG. 5B includes eight memory cells 450, 452, 454, 456, 458, 460, 462, and 464. Between each of the floating gate stacks are source/drain region 466. Drain side select gate 446 connects the NAND string to bit line contact 472. Source side select gate 448 connects the NAND string to the source line 442. Drain side select gate 446 receives Vsgd, which is at or near the power supply voltage Vdd. To inhibit memory cell 458, bit line contact 472 receives the power supply voltage Vdd (or another suitable inhibit voltage) via the corresponding bit line. As discussed above with respect to FIG. 4B, select gate 424 will cut off when the NAND string voltage gets high enough, therefore, allowing channel 470 to become highly boosted. Similarly, because memory cell 456 is receiving zero volts at its control gate, it also will cut off allowing channel 468 to become boosted. However, because some of the memory cells 450, 452 or 454 may be programmed, the boosting in channel 468 is likely to be lower than the boosting in channel in 470.
Although the two channel areas are separated by the word line connected to zero volts, this does not mean that the isolation between the two areas is perfect. The isolation properties of memory cell 456, referred to as the isolation cell, depend on the data that is programmed in that memory cell.
When the isolation cell is in the erased state, the threshold voltage is negative. As a result, some boosted charge can be transferred from the higher boosted range side to the lower boosted source side (e.g., from highly boosted channel 470 to lower boosted channel 468). So, when the threshold voltage of memory cell 456 is negative, the transistor may not turn off even when zero volts is applied to the word line. If the memory cell is on, the NAND string is not initially operating in EASB mode. Rather the string is operating in a mode that is similar to self boosting, which has the problems discussed above. Once the source side boosted potential reaches a certain level, the isolation cell will automatically be cut-off. This occurs when the source side boosted potential becomes higher than the absolute value of the threshold voltage of the cell. The probability that this type of leakage occurs can be decreased by using two or more isolation word lines instead of only one. For example, a technique called Revised Erased Area Self Boost (REASB) uses two or more isolation word lines that can all be biased differently. For example, the immediate source side neighbor word line (e.g. word line for memory cell 456) is at a low voltage (e.g. a similar voltage as Vdd). Two word lines over from the word line being programmed (e.g. word line for memory cell 454) is set at zero volts. For example, looking at FIG. 5B, memory cell 456 would receive Vdd at its word line and memory 454 would receive zero volts at its word line. For more information, see U.S. patent application Ser. No. 10/774,014, “Self-Boosting System For Flash Memory Cells,” filed on Feb. 6, 2004 (now U.S. Pat. No. 7,161,833), incorporated herein by reference in its entirety.
When the isolation cell (e.g., memory cell 456) is programmed to a high threshold voltage state, such as around three volts, the isolation will be very good since the transistor is in the off state at all times during the operation. However, even in that state, some leakage from the drain side boosted area 470 to the lower boosted source side area 468 may still occur due to punch-through between the drain and source of memory cell 456. This will become especially more severe for future generation NAND devices since the channel lengths will become shorter and, thus, punch-through can occur at lower voltage differences. To avoid punch-through, the P-type doping concentration in the channel area under the memory cell should be increased or two or more word lines should be biased to zero volts or near zero volts (as per the REASB method discussed above).
Another effect that can occur when the isolation cell is in a high threshold voltage state is Gate Induced Drain Leakage (GIDL), which is also referred to as Band-To-Band-Tunneling. When the isolation cells are in the high threshold voltage state, the floating gate potential of that cell is lower than zero volts and the drain side of the isolation cell is boosted to a high potential. As a result, a very high vertical electric field is present near the drain area of the isolation cell. This high electric field may cause Band-To-Band-Tunneling as depicted in FIG. 6. Note, however, that GIDL or Band-To-Band tunneling may not be the only breakdown or leakage mechanism that can occur on the drain side of the isolation cell. Breakdown or leakage at the side of the drain area due to a strong lateral electric field, possibly further enhanced by the strong vertical electric field due to the negatively biased gate, may also occur. Furthermore, breakdown or leakage at the bottom of the drain junction (drain to P-well) may occur as well. All these breakdown and/or leakage mechanisms will from hereon be referred to as boosting induced drain leakage (BIDL).
FIG. 6 shows a portion of the NAND string of FIG. 5B, with a zooming-in on the drain and a portion of the channel for isolation cell 456. Due to the vertical electric field discussed above, or due to the combination of a strong lateral and vertical field, there is a breakdown causing leakage. Holes are injected into the P-well at the channel from drain 466, and electrons leak into boosted channel 470. The leakage of electrons to boosted channel 470 can cause the boosted voltage to leak away prematurely, resulting in program disturb. Besides leakage of the boosted channel, the holes and electrons that were generated by the GIDL maybe accelerated in the high electric fields that are present in the device near the isolation cell. Hot holes and electrons maybe generated and injected in the gate oxides of the selected memory cell or other memory cells in the neighborhood of the selected memory cell. For example, hot hole injection may occur in the isolation cell since the gate of that cell is negatively biased which is favorable for hot hole injection. The injection of hot holes or electrons may cause undesired threshold voltage shifts in the memory cells, thus, causing program disturb or the gate oxides of the memory cells maybe degraded by the hot carriers causing other reliability problems. Boosting induced drain leakage should be reduced/suppressed as much as possible since it may degrade program disturb and other reliability characteristics of the memory cells.
As devices become smaller, the channel length of the individual memory cells become shorter. As channel lengths become shorter, it is harder to turn off memory cells because there is less isolation. To compensate, a higher concentration of P-type material can be used in the channel area. One example is to dope the channel using Boron. The more P-type material added, the greater the isolation between the source and drain regions. However, as more P-type material is introduced to the channel area, the electric field around the drain area during boosting, as discussed above, will get stronger. As the electric field increases, the chance that boosting induced drain leakage will occur increases as well. Thus, if there is not enough P-type material, the memory cell could experience punch-through and current can flow when it is not desired. On the other hand, too much P-type material could cause boosting induced drain leakage due to an increased electric field around or in the drain. Note that the required concentration of P-type material in the channel area is not only determined by punch-through during boosting, to maintain good or sufficiently good short channel behavior during a read operation is important as well. Too low of a concentration of P-type material in the channel will result in a memory cell threshold voltage that depends strongly on the length of the channel of the memory cell. This is undesired as certain variations in channel length are expected due to variations in the production process. The P-type doping concentration should be sufficiently high to ensure that a sufficiently high and stable threshold voltage can be maintained even when the channel length varies within a certain range.
Some prior art devices (i.e. MOS transistors used in logic devices) have attempted to reduce the sensitivity to channel length variations by doping the portions of the channel closest to the source and drain regions with Boron to create what is called a B-Halo type of doping profile (referred to as B-Halo from hereon).
FIGS. 7A-7D depict a summary of a process for making NAND flash memory, that can include a B-Halo implantation. FIG. 7A shows a P-well area being created by ion implantation techniques. This P-well can be formed by one implantation step or by a combination of multiple implantation steps. Typically, Boron is used for the P-well implantation, however, other materials or impurities can be used or added as well. The function of the P-well is to isolate NAND strings from another and to isolate NAND strings from neighboring devices such as peripheral transistors. The isolation of devices is usually done in combination with Shallow Trench Isolation (not depicted). During the P-well implantation, it is possible to define the doping profile in the channel area at the same time. Sometimes, a low energy Boron implantation is used to define the channel doping profile.
Subsequently, the stacked gate structures are formed. For a flash memory device, the stacked gate structure can include a tunnel oxide layer, floating gate, inter-poly isolation layer and control gate (and/or word line). FIG. 7B shows the device after the stacked gate structures are formed. FIG. 7B shows two NAND strings, referred to as even and odd strings. The even NAND string includes memory cells 380, source side select gate 384 and drain side select gate 386. The odd NAND string includes memory cells 382, source side select gate 388 and drain side select gate 390.
After forming the stacked gate structures, the source/drain regions are formed. FIG. 7C depicts an n-type implantation (e.g., Arsenic and/or Phosphorus) forming the source/drain regions. This implantation can be performed perpendicular to the Silicon substrate or angled as depicted in FIG. 7C. As part of the process depicted in FIG. 7C, a B-Halo implantation maybe added to reduce short channel effects.
Subsequently, if considered required, an additional implantation can be performed in the select gate areas, as depicted in FIG. 7D. In that case, the memory cells and part of the select gates are covered with a mask to prevent implantation of impurities in those regions. Only in the areas between the select gates are the extra impurities implanted. In some cases, additional Boron is implanted to increase the threshold voltage of the select gate transistors. The implantation can also be angled (not depicted). As the select gate transistors are used as isolation devices during read and write operations, their threshold voltage should be sufficiently high to achieve sufficient isolation.
A disadvantage of using a B-Halo type of structure for the memory cells, however, is that the transition from N-type to P-type material is steep since both a P-type and N-type material are implanted in the same area with relatively high doses. This steep doping profile may increase the boosting induced drain leakage due to the increased electric field around and in the drain, and therefore, result in degraded program disturb behavior. Even when the B-Halo technique is not used, scaling devices requires a higher P-type concentration in the channel area of the memory cells to avoid punch-through during boosting or threshold voltage variations during read (short channel effect), which will also result in increased electric field strengths around or in the drain and therefore increase the probability of boosting induced drain leakage. Thus, the requirements for scaling the memory cell and reducing boosting induced drain leakage are conflicting. To scale the memory cell, higher P-type concentrations are needed, while for boosting induced drain leakage reduction lower P-type and N-type concentrations are beneficial. As a result, scaling the memory cells can result in an increase in boosting induced drain leakage, and program disturb may deteriorate with each process generation.
Thus, there is a need for a better mechanism to prevent program disturb.